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| author | Arnd Bergmann <arnd@arndb.de> | 2024-07-09 11:53:48 +0300 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2024-07-09 11:53:48 +0300 |
| commit | 9e6b81559330f3c5fa1a5352af7e9682efe1f7df (patch) | |
| tree | b612cf81a19821b28ddc3bef7a346ba9f2ab51a9 /tools/perf/scripts/python/gecko.py | |
| parent | a4dd55f8c2c06e2741a74e49b95b6db0a772e345 (diff) | |
| parent | 3d41249c1dee0fa22ebd8d27aa0a280edf943a0e (diff) | |
| download | linux-9e6b81559330f3c5fa1a5352af7e9682efe1f7df.tar.xz | |
Merge tag 'riscv-cache-for-v6.11' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/drivers
RISC-V cache drivers for v6.11
StarFive:
A new driver for the cache controller on the jh8100, which didn't
implement Zicbom and thus needs an implementation of non-standard cache
management operations.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
* tag 'riscv-cache-for-v6.11' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
MAINTAINERS: add microchip soc binding directory to microchip soc driver entry
MAINTAINERS: add cache binding directory to cache driver entry
cache: Add StarFive StarLink cache management
dt-bindings: cache: Add docs for StarFive Starlink cache controller
Link: https://lore.kernel.org/r/20240707-whoever-undesired-c5f6e96ae403@spud
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'tools/perf/scripts/python/gecko.py')
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