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authorJoakim Zhang <qiangqing.zhang@nxp.com>2021-06-08 06:15:35 +0300
committerDavid S. Miller <davem@davemloft.net>2021-06-08 21:41:24 +0300
commit6813cc8cfdaf401476e1a007cec8ae338cefa573 (patch)
tree1c2c1b0943586e65847584348ff36080c61648d6 /tools/perf/scripts/python/futex-contention.py
parentd90db36a9e748c9d886df15f5e17b341f0e5bcd5 (diff)
downloadlinux-6813cc8cfdaf401476e1a007cec8ae338cefa573.tar.xz
net: phy: realtek: add delay to fix RXC generation issue
PHY will delay about 11.5ms to generate RXC clock when switching from power down to normal operation. Read/write registers would also cause RXC become unstable and stop for a while during this process. Realtek engineer suggests 15ms or more delay can workaround this issue. Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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