diff options
| author | Marijn Suijten <marijn.suijten@somainline.org> | 2024-04-17 02:57:41 +0300 |
|---|---|---|
| committer | Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | 2024-04-22 16:22:50 +0300 |
| commit | f12e0e12524a34bf145f7b80122e653ffe3d130a (patch) | |
| tree | 0bb928b56cc318ceda3b3fde58373d28f903ff07 /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | 87d322e9d25667bba50e8bb52e54b48e0d18b0af (diff) | |
| download | linux-f12e0e12524a34bf145f7b80122e653ffe3d130a.tar.xz | |
drm/msm/dsi: Print dual-DSI-adjusted pclk instead of original mode pclk
When dual-DSI (bonded DSI) was added in commit ed9976a09b48
("drm/msm/dsi: adjust dsi timing for dual dsi mode") some DBG() prints
were not updated, leading to print the original mode->clock rather
than the adjusted (typically the mode clock divided by two, though more
recently also adjusted for DSC compression) msm_host->pixel_clk_rate
which is passed to clk_set_rate() just below. Fix that by printing the
actual pixel_clk_rate that is being set.
Fixes: ed9976a09b48 ("drm/msm/dsi: adjust dsi timing for dual dsi mode")
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/589896/
Link: https://lore.kernel.org/r/20240417-drm-msm-initial-dualpipe-dsc-fixes-v1-1-78ae3ee9a697@somainline.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions