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authorConor Dooley <conor.dooley@microchip.com>2025-03-12 16:11:48 +0300
committerAlexandre Ghiti <alexghiti@rivosinc.com>2025-03-25 17:19:35 +0300
commite9f1d61a5e186092d3b8eaa411bb4a76622bf854 (patch)
tree9332997c37a1a64bb8d541a06de00a320edfa71f /tools/perf/scripts/python/exported-sql-viewer.py
parent534d813a06202c565b4a7e75a3e710db7155e6d3 (diff)
downloadlinux-e9f1d61a5e186092d3b8eaa411bb4a76622bf854.tar.xz
dt-bindings: riscv: add vector sub-extension dependencies
Section 33.18.2. Zve*: Vector Extensions for Embedded Processors in [1] says: | The Zve32f and Zve64x extensions depend on the Zve32x extension. The Zve64f extension depends | on the Zve32f and Zve64x extensions. The Zve64d extension depends on the Zve64f extension | The Zve32x extension depends on the Zicsr extension. The Zve32f and Zve64f extensions depend | upon the F extension | The Zve64d extension depends upon the D extension Apply these rules to the bindings to help prevent invalid combinations. Link: https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-isa-release-698e64a-2024-09-09 [1] Reviewed-by: Clément Léger <cleger@rivosinc.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20250312-banking-crestless-58f3259a5018@spud Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
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