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| author | Biju Das <biju.das.jz@bp.renesas.com> | 2021-11-12 11:10:01 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2021-11-19 13:34:56 +0300 |
| commit | d6dabaf678971733da56b2e84793348f714d42ff (patch) | |
| tree | ae7034a2b41bb18cf7ff0cbf0a9237f38d3cf5e8 /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | 86e122c0754951094a3857870ad9f4022e056f6b (diff) | |
| download | linux-d6dabaf678971733da56b2e84793348f714d42ff.tar.xz | |
clk: renesas: r9a07g044: Change core clock "I" from DEF_FIXED->DEF_DIV
Core clock "I" is sourced from CPG_PL1_DDIV divider as per HW manual
Rev.1.00.
This patch adds clock divider table "dtable_1_8" and switches to
DEF_DIV for "I" clock.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20211112081003.15453-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions