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authorDevarsh Thakkar <devarsht@ti.com>2024-02-16 09:24:23 +0300
committerTomi Valkeinen <tomi.valkeinen@ideasonboard.com>2024-02-19 14:12:50 +0300
commitb59dcca97bf052341b9ac28b1ee1af46498b8833 (patch)
tree4d92f4ab236a2c75fb67a8368d9f118ee4c1ce47 /tools/perf/scripts/python/exported-sql-viewer.py
parentb7f9b9b67ebdaff4847f13c721228e63b5c13222 (diff)
downloadlinux-b59dcca97bf052341b9ac28b1ee1af46498b8833.tar.xz
dt-bindings: display: ti,am65x-dss: Add support for common1 region
TI keystone display subsystem present in AM65, AM62 and AM62A SoC support two separate register spaces namely "common" and "common1" which can be used by two separate hosts to program the display controller as described in respective Technical Reference Manuals [1]. The common1 register space has similar set of configuration registers as supported in common register space except the global configuration registers which are exclusive to common region. This adds binding for "common1" register region too as supported by the hardware. [1]: AM62x TRM: https://www.ti.com/lit/pdf/spruiv7 (Section 14.8.9.1 DSS Registers) AM65x TRM: https://www.ti.com/lit/pdf/spruid7 (Section 12.6.5 DSS Registers) AM62A TRM: https://www.ti.com/lit/pdf/spruj16 (Section 14.9.9 Display Subsystem Registers) Fixes: 2d8730f1021f ("dt-bindings: display: ti,am65x-dss: Add dt-schema yaml binding") Signed-off-by: Devarsh Thakkar <devarsht@ti.com> Reviewed-by: Aradhya Bhatia <a-bhatia1@ti.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240216062426.4170528-2-devarsht@ti.com
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