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authorConor Dooley <conor.dooley@microchip.com>2025-03-12 16:11:44 +0300
committerAlexandre Ghiti <alexghiti@rivosinc.com>2025-03-25 17:10:08 +0300
commit9324571e9eea231321acf0a3d0fbc85a6e0f6ff6 (patch)
tree73a7c953820cd4e174ae90523b6db014739a6dba /tools/perf/scripts/python/exported-sql-viewer.py
parent4701f33a10702d5fc577c32434eb62adde0a1ae1 (diff)
downloadlinux-9324571e9eea231321acf0a3d0fbc85a6e0f6ff6.tar.xz
RISC-V: add vector extension validation checks
Using Clement's new validation callbacks, support checking that dependencies have been satisfied for the vector extensions. From the kernel's perfective, it's not required to differentiate between the conditions for all the various vector subsets - it's the firmware's job to not report impossible combinations. Instead, the kernel only has to check that the correct config options are enabled and to enforce its requirement of the d extension being present for FPU support. Since vector will now be disabled proactively, there's no need to clear the bit in elf_hwcap in riscv_fill_hwcap() any longer. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com> Link: https://lore.kernel.org/r/20250312-eclair-affluent-55b098c3602b@spud Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
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