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author | Palmer Dabbelt <palmer@rivosinc.com> | 2024-11-11 18:35:09 +0300 |
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committer | Palmer Dabbelt <palmer@rivosinc.com> | 2024-11-11 18:35:09 +0300 |
commit | 64f7b77f0bd9271861ed9e410e9856b6b0b21c48 (patch) | |
tree | e769c7d3d612098540221cfe79b6575f20db3a3c /tools/perf/scripts/python/exported-sql-viewer.py | |
parent | 075fde581896bde171d43a994df8617b9728eae7 (diff) | |
parent | ab83647fadae2f1f723119dc066b39a461d6d288 (diff) | |
download | linux-64f7b77f0bd9271861ed9e410e9856b6b0b21c48.tar.xz |
Merge patch series "Zacas/Zabha support and qspinlocks"
Alexandre Ghiti <alexghiti@rivosinc.com> says:
This implements [cmp]xchgXX() macros using Zacas and Zabha extensions
and finally uses those newly introduced macros to add support for
qspinlocks: note that this implementation of qspinlocks satisfies the
forward progress guarantee.
It also uses Ziccrse to provide the qspinlock implementation.
Thanks to Guo and Leonardo for their work!
* b4-shazam-merge: (1314 commits)
riscv: Add qspinlock support
dt-bindings: riscv: Add Ziccrse ISA extension description
riscv: Add ISA extension parsing for Ziccrse
asm-generic: ticket-lock: Add separate ticket-lock.h
asm-generic: ticket-lock: Reuse arch_spinlock_t of qspinlock
riscv: Implement xchg8/16() using Zabha
riscv: Implement arch_cmpxchg128() using Zacas
riscv: Improve zacas fully-ordered cmpxchg()
riscv: Implement cmpxchg8/16() using Zabha
dt-bindings: riscv: Add Zabha ISA extension description
riscv: Implement cmpxchg32/64() using Zacas
riscv: Do not fail to build on byte/halfword operations with Zawrs
riscv: Move cpufeature.h macros into their own header
Link: https://lore.kernel.org/r/20241103145153.105097-1-alexghiti@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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