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| author | Neil Armstrong <neil.armstrong@linaro.org> | 2024-03-22 12:42:41 +0300 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2024-04-05 20:04:00 +0300 |
| commit | 5cee04a8369049b92d52995e320abff18dfeda44 (patch) | |
| tree | 7ea484963d799d74d7cb1e5d3dc88ec7edb4acde /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | 583ca9ccfa806605ae1391aafa3f78a8a2cc0b48 (diff) | |
| download | linux-5cee04a8369049b92d52995e320abff18dfeda44.tar.xz | |
phy: qcom: qmp-pcie: register PHY AUX clock for SM8[456]50 4x2 PCIe PHY
The PCIe Gen4x2 PHY found in the SM8[456]50 SoCs have a second clock,
enable this second clock by setting the proper 20MHz hardware rate in
the Gen4x2 SM8[456]50 aux_clock_rate config fields.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20240322-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v2-4-3ec0a966d52f@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions