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authorAlex Deucher <alexander.deucher@amd.com>2020-09-28 21:16:25 +0300
committerAlex Deucher <alexander.deucher@amd.com>2020-09-30 00:09:59 +0300
commit3c26d0314c10ceb77511e2cc81894001d488c1d0 (patch)
treedeae39a868d0aa6cb06bbb325534eae2617ab495 /tools/perf/scripts/python/exported-sql-viewer.py
parenta39d0d7bdf8c21ac7645c02e9676b5cb2b804c31 (diff)
downloadlinux-3c26d0314c10ceb77511e2cc81894001d488c1d0.tar.xz
drm/amdgpu/swsmu/smu12: fix force clock handling for mclk
The state array is in the reverse order compared to other asics (high to low rather than low to high). Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1313 Reviewed-by: Prike Liang <Prike.Liang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
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