diff options
| author | Dave Jiang <dave.jiang@intel.com> | 2023-02-14 20:00:24 +0300 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2023-02-15 01:12:54 +0300 |
| commit | 248529edc86f8d7d390a15a86bd1904951311665 (patch) | |
| tree | 0eb11c11d179bca096a9c8539a3dd02bbe39c1d3 /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | 1922a6dc0502ed3fd0786f57cc9e5f515c902009 (diff) | |
| download | linux-248529edc86f8d7d390a15a86bd1904951311665.tar.xz | |
cxl: add RAS status unmasking for CXL
By default the CXL RAS mask registers bits are defaulted to 1's and
suppress all error reporting. If the kernel has negotiated ownership
of error handling for CXL then unmask the mask registers by writing 0s.
PCI_EXP_DEVCTL capability is checked to see uncorrectable or correctable
errors bits are set before unmasking the respective errors.
Acked-by: Bjorn Helgaas <bhelgaas@google.com> # pci_regs.h
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Link: https://lore.kernel.org/r/167639402301.778884.12556849214955646539.stgit@djiang5-mobl3.local
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions