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author | Jinjie Ruan <ruanjinjie@huawei.com> | 2024-07-03 05:27:32 +0300 |
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committer | Palmer Dabbelt <palmer@rivosinc.com> | 2024-08-15 03:44:34 +0300 |
commit | 0e3f3649d44bf1b388a7613ade14c29cbdedf075 (patch) | |
tree | cd5bc8fddb6ec66a6aa96edd492550a9404049c3 /tools/perf/scripts/python/exported-sql-viewer.py | |
parent | c6ebf2c528470a09be77d0d9df2c6617ea037ac5 (diff) | |
download | linux-0e3f3649d44bf1b388a7613ade14c29cbdedf075.tar.xz |
riscv: Enable generic CPU vulnerabilites support
Currently x86, ARM and ARM64 support generic CPU vulnerabilites, but
RISC-V not, such as:
# cd /sys/devices/system/cpu/vulnerabilities/
x86:
# cat spec_store_bypass
Mitigation: Speculative Store Bypass disabled via prctl and seccomp
# cat meltdown
Not affected
ARM64:
# cat spec_store_bypass
Mitigation: Speculative Store Bypass disabled via prctl and seccomp
# cat meltdown
Mitigation: PTI
RISC-V:
# cat /sys/devices/system/cpu/vulnerabilities
# ... No such file or directory
As SiFive RISC-V Core IP offerings are not affected by Meltdown and
Spectre, it can use the default weak function as below:
# cat spec_store_bypass
Not affected
# cat meltdown
Not affected
Link: https://www.sifive.cn/blog/sifive-statement-on-meltdown-and-spectre
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Link: https://lore.kernel.org/r/20240703022732.2068316-1-ruanjinjie@huawei.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions