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authorSamuel Holland <samuel.holland@sifive.com>2024-10-16 23:27:45 +0300
committerPalmer Dabbelt <palmer@rivosinc.com>2024-10-25 00:12:55 +0300
commit09d6775f503b393d0457c7126aa43208e1724004 (patch)
tree87c43823074a94f43def3320e1169d059818ff8c /tools/perf/scripts/python/exported-sql-viewer.py
parent29eedc7d1587f42f33ae209be45c89c424ee9c00 (diff)
downloadlinux-09d6775f503b393d0457c7126aa43208e1724004.tar.xz
riscv: Add support for userspace pointer masking
RISC-V supports pointer masking with a variable number of tag bits (which is called "PMLEN" in the specification) and which is configured at the next higher privilege level. Wire up the PR_SET_TAGGED_ADDR_CTRL and PR_GET_TAGGED_ADDR_CTRL prctls so userspace can request a lower bound on the number of tag bits and determine the actual number of tag bits. As with arm64's PR_TAGGED_ADDR_ENABLE, the pointer masking configuration is thread-scoped, inherited on clone() and fork() and cleared on execve(). Reviewed-by: Charlie Jenkins <charlie@rivosinc.com> Tested-by: Charlie Jenkins <charlie@rivosinc.com> Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Link: https://lore.kernel.org/r/20241016202814.4061541-5-samuel.holland@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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