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| author | Matthew Brost <matthew.brost@intel.com> | 2021-10-29 01:42:24 +0300 |
|---|---|---|
| committer | John Harrison <John.C.Harrison@Intel.com> | 2021-11-10 00:54:24 +0300 |
| commit | 03f060b73f9ad9555f6251cac21c692df8112a68 (patch) | |
| tree | 74d85f675957f333424a9e305ae72825c5c9e722 /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | c10a652e239e21492525fab295dc2fc303338ef1 (diff) | |
| download | linux-03f060b73f9ad9555f6251cac21c692df8112a68.tar.xz | |
drm/i915/resets: Don't set / test for per-engine reset bits with GuC submission
Don't set, test for, or clear per-engine reset bits with GuC submission
as the GuC owns the per engine resets not the i915. Setting, testing
for, and clearing these bits is causing issues with the hangcheck
selftest. Rather than change to test to not use these bits, rip the use
of these bits out from the reset code.
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: John Harrison <John.C.Harrison@Intel.com>
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211028224224.32693-1-matthew.brost@intel.com
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions