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| author | Chen Wang <unicorn_wang@outlook.com> | 2024-08-05 12:19:04 +0300 |
|---|---|---|
| committer | Ulf Hansson <ulf.hansson@linaro.org> | 2024-08-26 14:01:50 +0300 |
| commit | fc7b91683edbba4eab6c454f89e41aa56ea614e2 (patch) | |
| tree | b21f9968c87a3c37b12d113478c7fe61f6e29b22 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | a2e34ac156a0ff7bc0b22ea21a92b411636b7b50 (diff) | |
| download | linux-fc7b91683edbba4eab6c454f89e41aa56ea614e2.tar.xz | |
dt-bindings: mmc: sdhci-of-dwcmhsc: Add Sophgo SG2042 support
SG2042 use Synopsys dwcnshc IP for SD/eMMC controllers.
SG2042 defines 3 clocks for SD/eMMC controllers.
- EMMC_100M/SD_100M for cclk(Card clocks in DWC_mshc), so reuse
existing "core".
- AXI_EMMC/AXI_SD for aclk/hclk(Bus interface clocks in DWC_mshc)
and blck(Core Base Clock in DWC_mshc), these 3 clocks share one
source, so reuse existing "bus".
- 100K_EMMC/100K_SD for cqetmclk(Timer clocks in DWC_mshc), so reuse
existing "timer" which was added for rockchip specified.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/9ca450097e5389a38bcd7d8ddf863766df4cea10.1722847198.git.unicorn_wang@outlook.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions