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| author | Lu Baolu <baolu.lu@linux.intel.com> | 2019-11-20 09:10:16 +0300 |
|---|---|---|
| committer | Joerg Roedel <jroedel@suse.de> | 2019-12-18 18:18:34 +0300 |
| commit | f81b846dcd9a1e6d120f73970a9a98b7fcaaffba (patch) | |
| tree | b08f2a769d8053358f8582029a544cd733066fad /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | cde9319e884eb6267a0df446f3c131fe1108defb (diff) | |
| download | linux-f81b846dcd9a1e6d120f73970a9a98b7fcaaffba.tar.xz | |
iommu/vt-d: Remove incorrect PSI capability check
The PSI (Page Selective Invalidation) bit in the capability register
is only valid for second-level translation. Intel IOMMU supporting
scalable mode must support page/address selective IOTLB invalidation
for first-level translation. Remove the PSI capability check in SVA
cache invalidation code.
Fixes: 8744daf4b0699 ("iommu/vt-d: Remove global page flush support")
Cc: Jacob Pan <jacob.jun.pan@linux.intel.com>
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions