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| author | George Shen <george.shen@amd.com> | 2023-10-20 05:03:41 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2023-11-07 19:17:11 +0300 |
| commit | f031ba12082cadd1d827b36ba1d2c76a2395134d (patch) | |
| tree | 74ec4f871977b75b64d2624356c3a871b780421f /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 8df0d7d33a58d9394bd1240205e393d5f2bab6c7 (diff) | |
| download | linux-f031ba12082cadd1d827b36ba1d2c76a2395134d.tar.xz | |
drm/amd/display: Update test link rate DPCD bit field to match spec
[Why]
An SCR was made to the DP2.0 spec that updated the bit field definition
for UHBR13.5 in the test link rate DPCD register.
[How]
Add new translation to match the SCR update. Keep old translation for
backwards compatibility.
Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Acked-by: Hersen Wu <hersenxs.wu@amd.com>
Signed-off-by: George Shen <george.shen@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions