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| author | Diogo Ivo <diogo.ivo@siemens.com> | 2024-04-03 13:48:11 +0300 |
|---|---|---|
| committer | Paolo Abeni <pabeni@redhat.com> | 2024-04-09 10:47:28 +0300 |
| commit | dc073430db8d3f28460ea3ec1901e34bf7e8c0f2 (patch) | |
| tree | 11d35d2b8b35d70bce3ea75a7aa57ae359e53d71 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 87c33315af380ca12a2e59ac94edad4fe0481b4c (diff) | |
| download | linux-dc073430db8d3f28460ea3ec1901e34bf7e8c0f2.tar.xz | |
dt-bindings: net: Add support for AM65x SR1.0 in ICSSG
Silicon Revision 1.0 of the AM65x came with a slightly different ICSSG
support: Only 2 PRUs per slice are available and instead 2 additional
DMA channels are used for management purposes. We have no restrictions
on specified PRUs, but the DMA channels need to be adjusted.
Co-developed-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Diogo Ivo <diogo.ivo@siemens.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: MD Danish Anwar <danishanwar@ti.com>
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions