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| author | Siddharth Vadapalli <s-vadapalli@ti.com> | 2023-03-15 09:23:06 +0300 |
|---|---|---|
| committer | Nishanth Menon <nm@ti.com> | 2023-03-20 23:32:20 +0300 |
| commit | d3bac98015da55866891054a2aeb42af7904fca8 (patch) | |
| tree | b66f962e78d0d847b743b30be88cec7f22cf5850 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 86e7de8bf908a03ac8fba4afeef25c54a1c2ef4a (diff) | |
| download | linux-d3bac98015da55866891054a2aeb42af7904fca8.tar.xz | |
arm64: dts: ti: j7200-main: Add CPSW5G nodes
TI's J7200 SoC has a 5 port Ethernet Switch instance with 4 external
ports and 1 host port, referred to as CPSW5G.
Add device-tree nodes for CPSW5G and disable it by default. Device-tree
overlays will be used to enable it.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20230315062307.1612220-4-s-vadapalli@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions