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| author | Kishon Vijay Abraham I <kishon@ti.com> | 2023-07-26 09:54:07 +0300 |
|---|---|---|
| committer | Nishanth Menon <nm@ti.com> | 2023-08-02 07:47:25 +0300 |
| commit | cac04e27f093c3cafdc10c03b6f50e1578ef8cbc (patch) | |
| tree | 5dcb4a362e45bad96fa013535681fd33bf521c1d /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | d6ffe1b4b8c1cdc0ae36b6bc65b11d336aecbb72 (diff) | |
| download | linux-cac04e27f093c3cafdc10c03b6f50e1578ef8cbc.tar.xz | |
arm64: dts: ti: k3-j721s2: Add overlay to enable main CPSW2G with GESI
The MAIN CPSW2G instance of CPSW on J721S2 SoC can be enabled with the GESI
Expansion Board connected to the J7 Common-Proc-Board. Use the overlay
to enable this.
Add alias for the MAIN CPSW2G port to enable kernel to fetch MAC address
directly from U-Boot.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Link: https://lore.kernel.org/r/20230726065407.378455-3-s-vadapalli@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions