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| author | Rohit Khaire <rohit.khaire@amd.com> | 2021-06-04 18:02:56 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2021-06-08 21:03:55 +0300 |
| commit | c247c021b13a2ce40dd9ed06f1e18044dcaefd37 (patch) | |
| tree | 20df74a67b30a58b93d950f2bce2b4e4c67e69a4 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | b71a52f44725a3efab9591621c9dd5f8f9f1b522 (diff) | |
| download | linux-c247c021b13a2ce40dd9ed06f1e18044dcaefd37.tar.xz | |
drm/amdgpu: Fix incorrect register offsets for Sienna Cichlid
RLC_CP_SCHEDULERS and RLC_SPARE_INT0 have different
offsets for Sienna Cichlid
Signed-off-by: Rohit Khaire <rohit.khaire@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions