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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2019-03-05 22:23:59 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2019-03-06 18:21:07 +0300 |
| commit | 7ca60367dd5256e277c1d7fda8b15dcb33afc65b (patch) | |
| tree | 7b2ab6f00be532c81caaccc4b379021bd7c980d9 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | a90e1948efb648f567444f87f3c19b2a0787affd (diff) | |
| download | linux-7ca60367dd5256e277c1d7fda8b15dcb33afc65b.tar.xz | |
drm/i915: Do not temporarily disable the DPLL on i830
The current code clears the DPLL register entirely when re-enabling
VGA mode temporarily during the DPLL enable sequence. On i830 we want to
keep the DPLLs on all the time, so let's not do this temporary
disabling.
The current code does work, so this doesn't seem super important.
But I prefer that we make the behaviour 100% consistent.
v2: Split this change the DVO 2x clocking patch
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> #v1
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190305192400.23121-1-ville.syrjala@linux.intel.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions