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| author | Biju Das <biju.das.jz@bp.renesas.com> | 2023-03-30 14:16:28 +0300 |
|---|---|---|
| committer | Lee Jones <lee@kernel.org> | 2023-04-26 13:40:34 +0300 |
| commit | 654c293e1687b31819f9bf1ac71b5a85a8053210 (patch) | |
| tree | 0abce928409e1c44d7964c540f5ec76d6b576306 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 0a9d6b54297e216199cbfd08c5e6a35cce152477 (diff) | |
| download | linux-654c293e1687b31819f9bf1ac71b5a85a8053210.tar.xz | |
mfd: Add Renesas RZ/G2L MTU3a core driver
The RZ/G2L multi-function timer pulse unit 3 (MTU3a) is embedded in
the Renesas RZ/G2L family SoCs. It consists of eight 16-bit timer
channels and one 32-bit timer channel. It supports the following
functions
- Counter
- Timer
- PWM
The 8/16/32 bit registers are mixed in each channel.
Add MTU3a core driver for RZ/G2L SoC. The core driver shares the
clk and channel register access for the other child devices like
Counter, PWM and Clock event.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20230330111632.169434-3-biju.das.jz@bp.renesas.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions