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author | David S. Miller <davem@davemloft.net> | 2023-02-03 12:19:41 +0300 |
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committer | David S. Miller <davem@davemloft.net> | 2023-02-03 12:19:41 +0300 |
commit | 64e09d04b9562eb1cae8bd06afff0f73ae315102 (patch) | |
tree | ffb4fb4daaa733d00a8b1fb29d0fa76975071fc4 /tools/perf/scripts/python/export-to-sqlite.py | |
parent | 2798e36dc233a409a5d3f26f73029596dc504020 (diff) | |
parent | 04c77d9130b693e56a477364af1e1be4379b1b49 (diff) | |
download | linux-64e09d04b9562eb1cae8bd06afff0f73ae315102.tar.xz |
Merge branch 'rswitch-SERDES-PHY-init'
Yoshihiro Shimoda says:
====================
net: renesas: rswitch: Modify initialization for SERDES and PHY
- My platform has the 88x2110.
- The MACTYPE setting of strap pin on the platform is SXGMII.
- However, we realized that the SoC cannot communicate the PHY with SXGMII
because of mismatching hardware specification.
- We have a lot of boards which mismatch the MACTYPE setting.
So, I would like to change the MACTYPE as SGMII by software for the platform.
The patch [1/5] sets phydev->host_interfaces by phylink for Marvell PHY
driver (marvell10g) to initialize the MACTYPE.
- The patch [1/5] siplifies the rswitch driver.
- The patch [2/5] converts to phy_device from phylink.
- The patch [3/5] sets phydev->host_interfaces from this driver without
any new functions of phylib.
- The patch [4/5] adds phy_power_on() calling to initialize the Ethernet
SERDES PHY driver (r8a779f0-eth-serdes) for each channel.
- The patch [5/5] adds "max-speed" handling.
Changes from v4:
https://lore.kernel.org/all/20230127142621.1761278-1-yoshihiro.shimoda.uh@renesas.com/
- No modification of phylink API.
- Convert to phylib instead of phylink.
- Add "max-speed" handling.
Changes from v3:
https://lore.kernel.org/all/20230127014812.1656340-1-yoshihiro.shimoda.uh@renesas.com/
- Keep a pointer of "port" and more simplify the code.
====================
Signed-off-by: David S. Miller <davem@davemloft.net>
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