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| author | Aric Cyr <aric.cyr@amd.com> | 2023-10-30 04:22:37 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2023-11-07 20:03:30 +0300 |
| commit | 5c10147464fafbd3850d1f276a75a8825ecbbc0d (patch) | |
| tree | 91d1c692d8d843f83ffa0a433aebf851a0745017 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | fecbaa0a79adaa632e406ee5cffe5751e2d44fcb (diff) | |
| download | linux-5c10147464fafbd3850d1f276a75a8825ecbbc0d.tar.xz | |
drm/amd/display: Promote DAL to 3.2.259
Summary:
- Enable DCN35 physymclk root clock gating
- Fix DP automation test pattern bug
- Disable OTG for mode timing switch on DCN35
- Refactor DML2
- Revert Fix handling duplicate planes on one stream
- Revert Enable DCN clock gating
- Implement cursor P-State allow for SubVP
- Optimize pipe otg allocation
- Save and restore mall state while switching from ODM to Subvp
Acked-by: Hersen Wu <hersenxs.wu@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions