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| author | Lu Baolu <baolu.lu@linux.intel.com> | 2024-04-24 10:16:41 +0300 |
|---|---|---|
| committer | Joerg Roedel <jroedel@suse.de> | 2024-04-26 12:57:47 +0300 |
| commit | 4f609dbff51b3c98d5fc841758a20be74ab3f132 (patch) | |
| tree | 3e616f6949273678fbc83119d00393d890f76c6a /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 8ebc22366ed8bb2cbcf215bfa3fabb4f36d10a91 (diff) | |
| download | linux-4f609dbff51b3c98d5fc841758a20be74ab3f132.tar.xz | |
iommu/vt-d: Use cache helpers in arch_invalidate_secondary_tlbs
The arch_invalidate_secondary_tlbs callback is called in the SVA mm
notification path. It invalidates all or a range of caches after the
CPU page table is modified. Use the cache tag helps in this path.
The mm_types defines vm_end as the first byte after the end address
which is different from the iommu gather API, hence convert the end
parameter from mm_types to iommu gather scheme before calling the
cache_tag helper.
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
Link: https://lore.kernel.org/r/20240416080656.60968-10-baolu.lu@linux.intel.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions