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| author | Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> | 2021-01-11 15:04:09 +0300 |
|---|---|---|
| committer | Rob Clark <robdclark@chromium.org> | 2021-01-31 22:34:34 +0300 |
| commit | 45596f254061dae8ee04021c7146b362501a02ee (patch) | |
| tree | 23d00f50b7dbb7c884ea7bf70a81774b0a1361ca /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 276619c0923f8fa6a82e60edb88a82468645362d (diff) | |
| download | linux-45596f254061dae8ee04021c7146b362501a02ee.tar.xz | |
drm/msm/a6xx: Create an A6XX GPU specific address space
A6XX GPUs have support for last level cache(LLC) also known
as system cache and need to set the bus attributes to
use it. Currently we use a generic adreno iommu address space
implementation which are also used by older GPU generations
which do not have LLC and might introduce issues accidentally
and is not clean in a way that anymore additions of GPUs
supporting LLC would have to be guarded under ifdefs. So keep
the generic code separate and make the address space creation
A6XX specific. We also have a helper to set the llc attributes
so that if the newer GPU generations do support them, we can
use it instead of open coding domain attribute setting for each
GPU.
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions