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| author | Imre Deak <imre.deak@intel.com> | 2022-09-02 09:03:37 +0300 |
|---|---|---|
| committer | Radhakrishna Sripada <radhakrishna.sripada@intel.com> | 2022-09-13 01:22:04 +0300 |
| commit | 40151be79668232187b1ba7e00983be76a7f5845 (patch) | |
| tree | 0f43daadb231aab36cfc42b031b75febfc58da3c /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | e5d464d02f0681c4677c0bb5f6c0a70c8be78ab6 (diff) | |
| download | linux-40151be79668232187b1ba7e00983be76a7f5845.tar.xz | |
drm/i915/mtl: Add display power wells
Add support for display power wells on MTL. The differences from XE_LPD:
- The AUX HW block is moved to the PICA block, where the registers are on
an always-on power well and the functionality needs to be powered on/off
via the AUX_CH_CTL register: [1], [2]
- The DDI IO power on/off programming sequence is moved to the PHY PLL
enable/disable sequence. [3], [4], [5]
Bspec: [1] 49233, [2] 65247, [3] 64568, [4] 65451, [5] 65450
v2:
- Update the comment in aux power well enable
- Reuse the noop sync fn for aux sync.
- Use REG_BIT for new register bit definitions
Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220902060342.151824-7-radhakrishna.sripada@intel.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions