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authorJim Quinlan <jquinlan@broadcom.com>2020-09-11 20:52:28 +0300
committerLorenzo Pieralisi <lorenzo.pieralisi@arm.com>2020-10-02 14:40:40 +0300
commit3baec684a531866a39d9c20a0227aa272827a6ac (patch)
tree7b342c70aa021da3fbe3cf522bc73bedbeabbc94 /tools/perf/scripts/python/export-to-sqlite.py
parent52ded9e4f07b7b608344c5bbef59e31f7b39cb79 (diff)
downloadlinux-3baec684a531866a39d9c20a0227aa272827a6ac.tar.xz
PCI: brcmstb: Accommodate MSI for older chips
Older BrcmSTB chips do not have a separate register for MSI interrupts; the MSIs are in a register that also contains unrelated interrupts. In addition, the interrupts lie in bits [31..24] for these legacy chips. This commit provides common code for both legacy and non-legacy MSI interrupt registers. Link: https://lore.kernel.org/r/20200911175232.19016-9-james.quinlan@broadcom.com Signed-off-by: Jim Quinlan <jquinlan@broadcom.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Florian Fainelli <f.fainelli@gmail.com>
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