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| author | Jernej Skrabec <jernej.skrabec@siol.net> | 2019-11-10 09:30:01 +0300 |
|---|---|---|
| committer | Mauro Carvalho Chehab <mchehab@kernel.org> | 2019-11-10 09:30:01 +0300 |
| commit | 3aef46bd5bf24a845e05d2531ed61f53ee8c7797 (patch) | |
| tree | 82b371dcf63967e1278788de01ce6274765dac45 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | df4a3e7f88e3b0d7ae46d70b9ff8e3c0ea730785 (diff) | |
| download | linux-3aef46bd5bf24a845e05d2531ed61f53ee8c7797.tar.xz | |
media: cedrus: Properly signal size in mode register
Mode register also holds information if video width is bigger than 2048
and if it is equal to 4096.
Rework cedrus_engine_enable() to properly signal this properties.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Acked-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions