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| author | Marek Vasut <marex@denx.de> | 2018-05-01 06:39:51 +0300 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2018-05-14 14:51:11 +0300 |
| commit | 3ace822ad4b255eff7f56d2f452f7a8409b29b6d (patch) | |
| tree | ce54d5c477e31970bd638f22e106daf77ff2395e /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | a451debb4173bfe3b06d2ac926c4903eadc236d4 (diff) | |
| download | linux-3ace822ad4b255eff7f56d2f452f7a8409b29b6d.tar.xz | |
serial: 8250: Add missing rxtrig_bytes on Altera 16550 UART
The Altera 16550 UART core supports FCR Rx Trigger Level setting,
but the port definition in the driver is missing the rxtrig_bytes
array specifying the trigger levels. Add the array to make the Rx
Trigger Level setting available on this type of 16550 UART.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Thor Thayer <tthayer@opensource.altera.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions