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| author | Suraj Kandpal <suraj.kandpal@intel.com> | 2024-12-16 21:15:54 +0300 |
|---|---|---|
| committer | Tvrtko Ursulin <tursulin@ursulin.net> | 2024-12-24 12:41:00 +0300 |
| commit | 385a95cc72941c7f88630a7bc4176048cc03b395 (patch) | |
| tree | 65c45c31b36ba51e9d0809c871593df8aea97c1b /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 4bbf9020becbfd8fc2c3da790855b7042fad455b (diff) | |
| download | linux-385a95cc72941c7f88630a7bc4176048cc03b395.tar.xz | |
drm/i915/cx0_phy: Fix C10 pll programming sequence
According to spec VDR_CUSTOM_WIDTH register gets programmed after pll
specific VDR registers and TX Lane programming registers are done.
Moreover we only program into C10_VDR_CONTROL1 to update config and
setup master lane once all VDR registers are written into.
Bspec: 67636
Fixes: 51390cc0e00a ("drm/i915/mtl: Add Support for C10 PHY message bus and pll programming")
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241216181554.2861381-1-suraj.kandpal@intel.com
(cherry picked from commit f9d418552ba1e3a0e92487ff82eb515dab7516c0)
Signed-off-by: Tvrtko Ursulin <tursulin@ursulin.net>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions