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| author | Wolfram Sang <wsa+renesas@sang-engineering.com> | 2022-06-14 22:30:05 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-06-17 10:46:20 +0300 |
| commit | 1614c8624a48b9c9161b2071e9e727bf5a1817ef (patch) | |
| tree | 19fc1903c9048bfde6aeda25c6675f2026fa3c9e /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 40753144256b63b4e3fb9d80874605dda16ad713 (diff) | |
| download | linux-1614c8624a48b9c9161b2071e9e727bf5a1817ef.tar.xz | |
arm64: dts: renesas: spider-cpu: Enable SCIF0 on second connector
The schematics label it as SCIF0 debug port.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20220614193005.2652-1-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions