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| author | Abin Joseph <abin.joseph@amd.com> | 2024-08-08 13:00:24 +0300 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2024-08-29 20:16:16 +0300 |
| commit | 13113f750a4ae0b1770fa25dc94852977ebfb942 (patch) | |
| tree | 134ad51ccb15c1896af7b996ca8127af8842fbfc /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 36545c6a68b858671cfeb71df682e8cc58b082da (diff) | |
| download | linux-13113f750a4ae0b1770fa25dc94852977ebfb942.tar.xz | |
dmaengine: zynqmp_dma: Add support for AMD Versal Gen 2 DMA IP
ZynqMP DMA IP and AMD Versal Gen 2 DMA IP are similar but have different
interrupt register offset. Create a dedicated compatible string to
support Versal Gen 2 DMA IP with Irq register offset for interrupt
Enable/Disable/Status/Mask functionality.
Signed-off-by: Abin Joseph <abin.joseph@amd.com>
Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Link: https://lore.kernel.org/r/20240808100024.317497-3-abin.joseph@amd.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions