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| author | Conor Dooley <conor.dooley@microchip.com> | 2024-10-11 17:00:43 +0300 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2025-01-22 02:35:13 +0300 |
| commit | 04aa999eb96fdc8d3cf2b2d98363d6372befaef2 (patch) | |
| tree | 62a79b5535327b227db281503bdc751a620eb711 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 1390a33b3d04fdf6ba4e3e7082107a12027fc188 (diff) | |
| download | linux-04aa999eb96fdc8d3cf2b2d98363d6372befaef2.tar.xz | |
dt-bindings: PCI: microchip,pcie-host: Allow dma-noncoherent
PolarFire SoC may be configured in a way that requires non-coherent DMA
handling. On RISC-V, buses are coherent by default & the dma-noncoherent
property is required to denote buses or devices that are non-coherent.
Link: https://lore.kernel.org/r/20241011140043.1250030-4-daire.mcnamara@microchip.com
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Rob Herring <robh@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions