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| author | Omri Itach <omrii@marvell.com> | 2019-08-05 13:03:08 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2019-09-18 08:15:41 +0300 |
| commit | 0099dc446bb6a72ce24d4f86760d0f4fe4300138 (patch) | |
| tree | 9dd547a600631708e82db7f4626e960924bafe0e /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | cd016cb01835e0b9f62fb675b336fbded912dcb6 (diff) | |
| download | linux-0099dc446bb6a72ce24d4f86760d0f4fe4300138.tar.xz | |
clk: mvebu: ap806: add AP-DCLK (hclk) to system controller driver
Add dynamic AP-DCLK clock (hclk) to system controller driver. AP-DCLK
is half the rate of DDR clock, so its derrived from Sample At Reset
configuration. The clock frequency is required for AP806 AXI monitor
profiling feature.
Signed-off-by: Omri Itach <omrii@marvell.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lkml.kernel.org/r/20190805100310.29048-7-miquel.raynal@bootlin.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions