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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2024-02-26 13:59:45 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2024-03-26 11:30:36 +0300 |
| commit | 002b831076722f3a966a58defd1dc6976a46c109 (patch) | |
| tree | 969665e40234e2c927f2174c56d402d844b13bf1 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 4cece764965020c22cff7665b18a012006359095 (diff) | |
| download | linux-002b831076722f3a966a58defd1dc6976a46c109.tar.xz | |
dt-bindings: clock: r9a07g043-cpg: Annotate RZ/G2UL-only core clocks
The M2 (CRU main clock), M3 (LCDC Video Clock), and AT (Cortex-A55 Debug
clock) core clocks are only present on RZ/G2UL, not on RZ/Five.
Annotate this in the comments, like is already done for module clocks
and resets.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/ffcdcd479c76b92f67481836a33ec86e97f85634.1708944903.git.geert+renesas@glider.be
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
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