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| author | Arnd Bergmann <arnd@arndb.de> | 2022-11-30 19:41:56 +0300 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2022-11-30 19:42:23 +0300 |
| commit | f8a9f2704a0f9c41c639614b10aa19eab72eb4d2 (patch) | |
| tree | a468b6ce74afb01b1735386c614003c2ef2bf4cd /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | 9490ae741db64089819c263cb01bb195fcb554e6 (diff) | |
| parent | e567e58d6819adc002c57b81e16b88da24d3b4aa (diff) | |
| download | linux-f8a9f2704a0f9c41c639614b10aa19eab72eb4d2.tar.xz | |
Merge tag 'arm-soc/for-6.2/devicetree-arm64' of https://github.com/Broadcom/stblinux into soc/dt
This pull request contains Broadcom ARM64-based SoCs Device Tree updates
for 6.2, please pull the following:
- Rafal describes the timer/watchdog block for the BCM4908 and BCM6858
SoCs
- Krzysztof corrects invalid "reg" properties for the memory nodes that
were off by one digit
- Pierre updates a number of cache Device Tree node properties to be
schema compliant
* tag 'arm-soc/for-6.2/devicetree-arm64' of https://github.com/Broadcom/stblinux:
arm64: dts: Update cache properties for broadcom
arm64: dts: broadcom: trim addresses to 8 digits
arm64: dts: broadcom: bcmbca: bcm6858: add TWD block
arm64: dts: broadcom: bcmbca: bcm4908: add TWD block timer
Link: https://lore.kernel.org/r/20221129191755.542584-2-f.fainelli@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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