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authorSowjanya Komatineni <skomatineni@nvidia.com>2019-03-27 08:56:29 +0300
committerMark Brown <broonie@kernel.org>2019-04-01 11:39:42 +0300
commitf4ce428c41fb22e3ed55496dded94df44cb920fa (patch)
tree7a792e6e31c95ca8d9acd3512a2e31d7256feba7 /tools/perf/scripts/python/export-to-postgresql.py
parentc4fc9e5b28ff787e35137c2cc13316bb11d7657b (diff)
downloadlinux-f4ce428c41fb22e3ed55496dded94df44cb920fa.tar.xz
spi: tegra114: configure dma burst size to fifo trig level
Fixes: Configure DMA burst size to be same as SPI TX/RX trigger levels to avoid mismatch. SPI FIFO trigger levels are calculated based on the transfer length. So this patch moves DMA slave configuration to happen before start of DMAs. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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