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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2023-12-12 01:17:59 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2023-12-13 21:49:40 +0300 |
| commit | f23fe4d7d794c6d71dc6b8fdc510da2fc2174369 (patch) | |
| tree | 65429557e10a6ecf5c6bb4b93f9fec5b7749c2f5 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | e1a914aef28f39aec5f107f31478d95aff3ae6db (diff) | |
| download | linux-f23fe4d7d794c6d71dc6b8fdc510da2fc2174369.tar.xz | |
drm/i915/cdclk: Rewrite cdclk->voltage_level selection to use tables
The cdclk->voltage_level if ladders are hard to read, especially as
they're written the other way around compared to how bspec lists
the limits. Let's rewrite them to use simple arrays that gives us
the max cdclk for each voltage level.
v2: Bump the jsl/ehl max cdclk in the table to 652.8 MHz to
accommodate JSL machines in CI that boot with high cdclk
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231211221759.29725-1-ville.syrjala@linux.intel.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions