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authorAnkit Nautiyal <ankit.k.nautiyal@intel.com>2025-03-24 16:32:45 +0300
committerAnkit Nautiyal <ankit.k.nautiyal@intel.com>2025-03-25 18:47:25 +0300
commitcfd51309f8c89594ceac7d084c1e4eb4fbf9f142 (patch)
tree8bbf53268ad62a668345859425842b256663501b /tools/perf/scripts/python/export-to-postgresql.py
parent0ec46988ae6c5f3e6c4ccdf5e0abbc541b8d0680 (diff)
downloadlinux-cfd51309f8c89594ceac7d084c1e4eb4fbf9f142.tar.xz
drm/i915/vrr: Always use VRR timing generator for PTL+
Currently, the VRR timing generator is used only when VRR is enabled by userspace for sinks that support VRR. Starting with PTL+, gradually move away from the legacy timing generator and use the VRR timing generator for both variable and fixed timings. Note: For platforms where we always enable the VRR timing generator, the LRR fastset is not allowed to avoid live programming of vrr.guardband with VRR TG enabled. This effectively breaks the LRR fastset functionality for these platforms and needs to be addressed. v2: Use this for PTL for now to avoid losing LRR fastset for older platforms. (Ville) Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://lore.kernel.org/r/20250324133248.4071909-14-ankit.k.nautiyal@intel.com
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