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| author | Ankit Nautiyal <ankit.k.nautiyal@intel.com> | 2025-03-24 16:32:38 +0300 |
|---|---|---|
| committer | Ankit Nautiyal <ankit.k.nautiyal@intel.com> | 2025-03-25 18:47:24 +0300 |
| commit | be7f2ef5355370d0659b40f5a425af0f310e369a (patch) | |
| tree | 1490bc6b3c6eebb2c26f56b9e5284828b28bb24e /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | 660d1c6385b96c3985010589382c9c7849d4734c (diff) | |
| download | linux-be7f2ef5355370d0659b40f5a425af0f310e369a.tar.xz | |
drm/i915/vrr: Always set vrr vmax/vmin/flipline in vrr_{enable/disable}
For platforms for which vrr timing generator is always set, VRR_CTL
enable bit does not need to toggle, so modify the vrr_{enable/disable}
for this.
At the moment the helper intel_vrr_always_use_vrr_tg() return false for
all cases. This will be set later when all other bits are in place.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://lore.kernel.org/r/20250324133248.4071909-7-ankit.k.nautiyal@intel.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions