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authorRobert Hancock <robert.hancock@calian.com>2022-01-27 19:37:35 +0300
committerDavid S. Miller <davem@davemloft.net>2022-01-29 20:49:21 +0300
commit8b73fa3ae02b2401960de41b0454c0321377b203 (patch)
treebd8cf217b8bd94681ac55610c1c62bed3c312838 /tools/perf/scripts/python/export-to-postgresql.py
parentf4ea385a16c549753435601c8fb74e0ca12ad2d7 (diff)
downloadlinux-8b73fa3ae02b2401960de41b0454c0321377b203.tar.xz
net: macb: Added ZynqMP-specific initialization
The GEM controllers on ZynqMP were missing some initialization steps which are required in some cases when using SGMII mode, which uses the PS-GTR transceivers managed by the phy-zynqmp driver. The GEM core appears to need a hardware-level reset in order to work properly in SGMII mode in cases where the GT reference clock was not present at initial power-on. This can be done using a reset mapped to the zynqmp-reset driver in the device tree. Also, when in SGMII mode, the GEM driver needs to ensure the PHY is initialized and powered on. Signed-off-by: Robert Hancock <robert.hancock@calian.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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