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| author | Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> | 2024-11-18 08:49:32 +0300 |
|---|---|---|
| committer | Joerg Roedel <jroedel@suse.de> | 2024-12-18 11:37:39 +0300 |
| commit | 8b3f78733814b180089a400743b6f19d118aec62 (patch) | |
| tree | 1249833d4c562fbc5a533db746161bac2c124372 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | 7bea695ada0e84c40685551159068996cea29ef8 (diff) | |
| download | linux-8b3f78733814b180089a400743b6f19d118aec62.tar.xz | |
iommu/amd: Introduce helper function to update 256-bit DTE
The current implementation does not follow 128-bit write requirement
to update DTE as specified in the AMD I/O Virtualization Techonology
(IOMMU) Specification.
Therefore, modify the struct dev_table_entry to contain union of u128 data
array, and introduce a helper functions update_dte256() to update DTE using
two 128-bit cmpxchg operations to update 256-bit DTE with the modified
structure, and take into account the DTE[V, GV] bits when programming
the DTE to ensure proper order of DTE programming and flushing.
In addition, introduce a per-DTE spin_lock struct dev_data.dte_lock to
provide synchronization when updating the DTE to prevent cmpxchg128
failure.
Suggested-by: Jason Gunthorpe <jgg@nvidia.com>
Suggested-by: Uros Bizjak <ubizjak@gmail.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Reviewed-by: Uros Bizjak <ubizjak@gmail.com>
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Link: https://lore.kernel.org/r/20241118054937.5203-5-suravee.suthikulpanit@amd.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions