diff options
| author | Abel Vesa <abel.vesa@linaro.org> | 2024-10-09 14:07:23 +0300 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2024-10-16 23:23:43 +0300 |
| commit | 837c333f46df8ce6755ba82c53acb91948ec0072 (patch) | |
| tree | f7c0c1d791317451646b24c17c2b36f235dec0b4 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | 5d3d966400d0a094359009147d742b3926a2ea53 (diff) | |
| download | linux-837c333f46df8ce6755ba82c53acb91948ec0072.tar.xz | |
arm64: dts: qcom: x1e80100: Fix PCIe 6a lanes description
Fix the description and compatible for PCIe 6a, as it is in fact a
4-lanes controller and PHY, but it can also be used in 2-lanes mode. For
4-lanes mode, it uses the lanes provided by PCIe 6b. For 2-lanes mode,
PCIe 6a uses 2 lanes and then PCIe 6b uses the other 2 lanes. The number
of lanes in which the PHY should be configured depends on a TCSR register
value on each individual board.
Cc: stable+noautosel@kernel.org # Depends on pcie-qcom 16.0 GT/s support
Fixes: 5eb83fc10289 ("arm64: dts: qcom: x1e80100: Add PCIe nodes")
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Tested-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20241009-x1e80100-dts-fixes-pcie6a-v3-1-14a1163e691b@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions