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authorGrygorii Strashko <grygorii.strashko@ti.com>2019-11-18 15:20:16 +0300
committerTony Lindgren <tony@atomide.com>2019-11-20 20:42:33 +0300
commit6af0a549c25e0d02366aa95507bfe3cad2f7b68b (patch)
tree6d6f56161a8d6bc9cd08cbbbbc8e0328d2864ab1 /tools/perf/scripts/python/export-to-postgresql.py
parente415e4d2d506ce64ea540b4552654d1be0680a52 (diff)
downloadlinux-6af0a549c25e0d02366aa95507bfe3cad2f7b68b.tar.xz
ARM: dts: dra7: fix cpsw mdio fck clock
The DRA7 CPSW MDIO functional clock (gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0) is specified incorrectly, which is caused incorrect MDIO bus clock configuration MDCLK. The correct CPSW MDIO functional clock is gmac_main_clk (125MHz), which is the same as CPSW fck. Hence fix it. Fixes: 1faa415c9c6e ("ARM: dts: Add fck for cpsw mdio for omap variants") Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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