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| author | Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> | 2023-01-16 13:08:39 +0300 |
|---|---|---|
| committer | Lee Jones <lee@kernel.org> | 2023-01-27 13:36:29 +0300 |
| commit | 6052a005caf9cd484fe6368a31c736ac17ebaf66 (patch) | |
| tree | 0e52513de109f394ceab092678adefee5345f378 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | 603aed8ffd4c9cb633c05a514cfb5e8ca6b0751d (diff) | |
| download | linux-6052a005caf9cd484fe6368a31c736ac17ebaf66.tar.xz | |
mfd: intel-m10-bmc: Support multiple CSR register layouts
There are different addresses for the MAX10 CSR registers. Introducing
a new data structure m10bmc_csr_map for the register definition of
MAX10 CSR.
Provide the csr_map for SPI.
Co-developed-by: Tianfei zhang <tianfei.zhang@intel.com>
Signed-off-by: Tianfei zhang <tianfei.zhang@intel.com>
Reviewed-by: Russ Weight <russell.h.weight@intel.com>
Reviewed-by: Xu Yilun <yilun.xu@intel.com>
Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20230116100845.6153-6-ilpo.jarvinen@linux.intel.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
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