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| author | Dave Jiang <dave.jiang@intel.com> | 2024-04-03 18:47:13 +0300 |
|---|---|---|
| committer | Dave Jiang <dave.jiang@intel.com> | 2024-04-08 18:24:45 +0300 |
| commit | 592780b8391fe31f129ef4823c1513528f4dcb76 (patch) | |
| tree | 6bb2e157cc8e45cdc1d5f6f0bee7f7b82e06be65 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | 648dae58a830ecceea3b1bebf68432435980f137 (diff) | |
| download | linux-592780b8391fe31f129ef4823c1513528f4dcb76.tar.xz | |
cxl: Fix retrieving of access_coordinates in PCIe path
Current loop in cxl_endpoint_get_perf_coordinates() incorrectly assumes
the Root Port (RP) dport is the one with generic port access_coordinate.
However those coordinates are one level up in the Host Bridge (HB).
Current code causes the computation code to pick up 0s as the coordinates
and cause minimal bandwidth to result in 0.
Add check to skip RP when combining coordinates.
Fixes: 14a6960b3e92 ("cxl: Add helper function that calculate performance data for downstream ports")
Reported-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Dan Williams <dan.j.williams@intel.com>
Link: https://lore.kernel.org/r/20240403154844.3403859-3-dave.jiang@intel.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions