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authorRichard Schleich <rs@noreya.tech>2022-02-05 22:59:11 +0300
committerFlorian Fainelli <f.fainelli@gmail.com>2022-02-12 01:24:48 +0300
commit4c9b25077eb12534ab63dbefbab1ae6ff41c2144 (patch)
tree11ecb7e39b685fcf06f942bc70c02baca687212b /tools/perf/scripts/python/export-to-postgresql.py
parent618682b350990f8f1bee718949c4b3858711eb58 (diff)
downloadlinux-4c9b25077eb12534ab63dbefbab1ae6ff41c2144.tar.xz
ARM: dts: bcm2835/6: Add the missing L1/L2 cache information
This patch adds the cache info for the BCM2835 and BCM2836. However, while testing I noticed that this is not implemented for ARMv6/7. Basically arch/arm/kernel/cacheinfo.c and other topology related code is missing. Since the work is already done and this has no negative effects, I am submitting it for future/documentation purposes. Signed-off-by: Richard Schleich <rs@noreya.tech> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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