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| author | Jonathan Cameron <Jonathan.Cameron@huawei.com> | 2022-08-07 18:12:18 +0300 |
|---|---|---|
| committer | Jonathan Cameron <Jonathan.Cameron@huawei.com> | 2022-08-16 00:30:02 +0300 |
| commit | 4c0babbd978a98dfbdacbe078817ea9c953b3298 (patch) | |
| tree | 5272d882caabbb0b7c00f3049484b0f80d2a9608 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | 48a1319164d9339ad50a25085cad6b879fef9fbe (diff) | |
| download | linux-4c0babbd978a98dfbdacbe078817ea9c953b3298.tar.xz | |
staging: iio: resolver: ad2s1210: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition. As the tx[] an rx[] buffers are only used
in the same SPI exchanges, we should be safe with them on the same cacheline.
Hence only mark the first one __aligned(IIO_DMA_MINALIGN).
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Link: https://lore.kernel.org/r/20220807151218.656881-5-jic23@kernel.org
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions